The present invention relates to the field of testing electronic circuitry. Specifically, the present invention relates to a method which provides entry into test mode without impacting chip performance.
Testing a relatively complex circuit presents a number of and trade-offs with respect to the use of the circuit""s external pins. As pins are a relatively expensive component of modern circuits, it is desirable to keep the pin count low. Some conventional architectures dedicate selected pins to testing the circuit. While this simplifies the design, the pin count and hence the cost must be raised, if functionality is not to be sacrificed. Alternatively, the pin count can be kept constant, but at the expense of sacrificing circuit functionality due to selected pins being used for testing rather than another function. The fewer pins that the circuit has, the greater the problem of dedicating pins to testing becomes.
Testing circuits presents other problems as well, such as inadvertently entering test mode while the circuit is in its normal mode. Some conventional architectures used to test circuits allow the user to impose a supervoltage on one of the pins to trigger entry into the test mode. While this method may allow a pin to be used for more than just testing, this method is susceptible to noise accidentally causing entry to the test mode. For example, a user may generate electrostatic discharge while using a computer mouse device. The discharge may be transferred to the circuit, thus triggering entry into test mode. The result may be a program error requiring the user to reboot the computer.
Furthermore, the circuitry needed to support the above supervoltage technique may be complex. Thus, the cost of the circuit may be increased. Furthermore, the supervoltage circuitry may negatively impact issues such as circuit real estate and the designing of the circuit itself.
Still other problems are faced by the external testing device, which may have difficulty sending the analog waveform required by some circuits to put them into test mode.
Therefore, it would be advantageous to provide a method which allows getting into and out of test mode without disturbing normal operations. It would be further advantageous to provide a method of entering test mode of a circuit with a limited pin count. It would be further advantageous to provide such a method which does not require complex circuitry to enter circuit test mode. Finally, it would be advantageous to provide such a method for testing a circuit which minimizes the chance of accidentally entering test mode.
The present invention provides for a method for entering test mode without adding to the pin count. Furthermore, embodiments provide for a method for entering test mode while minimizing the chance of accidentally entering test mode. Furthermore, embodiments provide for such a method which does not require complex circuitry to enter circuit test mode. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period in which the voltages of the circuit ramp up, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode.
In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal.
In one embodiment, the negotiation to enter test mode takes place during a holdoff period after the lockout period. As the circuit is not useable for normal operation during the holdoff period, circuit performance is not impaired. In one embodiment, the test interface is serial. In yet another embodiment, the password is received by the test controller via one pin of the test interface while a clock signal is being received by the test controller via another pin of the test interface and the test interface is serial.
In one embodiment, if the password is not detected during the predetermined period of time the integrated circuit does not enter the test mode and a reset exit occurs, wherein normal circuit operation is entered.